1. Field of the Invention
The present invention relates, in general, to a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices and, more particularly, to a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices, which mainly performs cell and core tests and a direct current test that are most important and require the longest test time among memory tests, except for memory tests having complicated functions in a conventional memory module or memory component, for example, an alternating current margin test or timing generator, and which, in particular, simplifies the construction of conventional automated test equipment in a function test using test patterns and utilizes a programmable device, in which functions, such as pattern generation or comparison or signal application, are implemented on one chip, thus miniaturizing a semiconductor test apparatus and reducing the production cost thereof.
2. Description of the Related Art
Generally, a memory tester is designed and developed according to the status of a memory device, in particular, the development status of Dynamic Random Access Memory (DRAM) occupying considerable part of memory devices. Recently, DRAM has been developed into DRAM having an Extended Data Output (EDO) function, a Synchronous DRAM (SDRAM), Rambus DRAM (RDRAM), and, subsequently, Double Data Rate (DDR) DRAM.
In order to test such DRAM, a memory tester also requires high speed and high precision to correspond to the high speed of the memory. Further, a test duration increases as the capacity of memory increases, so that a test speed must also increase. Further, a miniaturized and economical memory tester must be implemented to reduce the cost of testing.
Typically, a memory tester is an apparatus used to test and inspect a memory component, or a memory module implemented in the form of a Single In-line Memory Module (SIMM) or Dual In-line Memory Module (DIMM). Such a memory tester determines whether a functional defect exists in a memory module or memory component before the memory module or memory component is mounted and used in an actual computer system, etc.
A memory tester can be classified into a hardware memory tester and a software diagnostic program executed in a Personal Computer (PC) environment. However, since the software diagnostic program diagnoses the status of a memory module or component that is mounted and used in an actual computer, the hardware memory tester is mainly used in a semiconductor memory manufacturing process.
Such a hardware memory tester can be classified into a high-end tester called Automated Test Equipment (ATE), a medium range memory tester and a low-end memory tester.
The ATE is typically used to execute a memory test process. In FIG. 1, a conceptual view of a semiconductor test apparatus that can be considered as a conventional typical memory tester is shown.
As shown in FIG. 1, a conventional semiconductor test apparatus 100 includes a power unit 110 for supplying a power voltage to a semiconductor device (module or component) 180 to be tested, a driver 120 for inputting a signal to the input unit of the semiconductor device 180, a comparator 130 for comparing a signal output from the output unit of the semiconductor device 180 with an expected signal, a pattern generator 140 for generating a signal sequence (test pattern) to be input to the semiconductor device 180 and the expected signal, a timing generator 150 for generating application timing for the signal to be input to the semiconductor device 180, and a Central Processing Unit (CPU) 160 which is a controller for controlling the above circuits. The CPU 160 is constructed to read a test program from an external storage device, generate and determine a test signal (test pattern) while analyzing the test program using an Operating System (OS), and perform a predetermined test. In the test apparatus 100, a separate Direct Current (DC) test circuit 170 may occasionally be installed to perform a DC test, such as the detection of the voltage level of the output unit.
Such a conventional memory tester is disadvantageous in that it performs a DC test for examining whether DC parameters are suitable for the digital operation of the circuit and an Alternating Current (AC) margin test related to the transfer delay time, set-up time and hold time of signals, has various functions, such as a timing generator, for these tests, and is produced using bulky and expensive dedicated equipment, such as a mainframe, thus increasing the production cost.
In a semiconductor manufacturing company, it is preferable to efficiently design expensive ATE so as to minimize the production cost of devices and improve competitiveness. Therefore, it is preferable to miniaturize ATE and reduce the production cost thereof by efficiently designing the ATE.